288 lines
6.1 KiB
C
288 lines
6.1 KiB
C
#include <riscv.h>
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#define __ASM __asm /* asm keyword for GNU Compiler */
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#define __INLINE inline /* inline keyword for GNU Compiler */
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/*********************************************************************
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* @fn RISCV_get_MSTATUS
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*
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* @brief Return the Machine Status Register
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*
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* @return mstatus value
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*/
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uint32_t RISCV_get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mstatus": "=r"(result));
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return (result);
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}
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uint32_t RISCV_get_set_MSTATUS(uint32_t value){
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uint32_t result;
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__ASM volatile("csrrw %0, mstatus, %1"
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: "=r"(result)
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:"r"(value)
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:"memory");
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MSTATUS
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*
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* @brief Set the Machine Status Register
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*
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* @param value - set mstatus value
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*
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* @return none
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*/
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void RISCV_set_MSTATUS(uint32_t value)
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{
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__ASM volatile("csrw mstatus, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MISA
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*
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* @brief Return the Machine ISA Register
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*
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* @return misa value
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*/
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uint32_t RISCV_get_MISA(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""misa" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set misa value
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*
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* @return none
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*/
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void RISCV_set_MISA(uint32_t value)
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{
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__ASM volatile("csrw misa, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MTVEC
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*
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* @brief Return the Machine Trap-Vector Base-Address Register
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*
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* @return mtvec value
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*/
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uint32_t RISCV_get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtvec": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MTVEC
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*
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* @brief Set the Machine Trap-Vector Base-Address Register
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*
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* @param value - set mtvec value
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*
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* @return none
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*/
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void RISCV_set_MTVEC(uint32_t value)
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{
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__ASM volatile("csrw mtvec, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MSCRATCH
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*
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* @brief Return the Machine Seratch Register
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*
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* @return mscratch value
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*/
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uint32_t RISCV_get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mscratch" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MSCRATCH
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*
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* @brief Set the Machine Seratch Register
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*
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* @param value - set mscratch value
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*
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* @return none
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*/
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void RISCV_set_MSCRATCH(uint32_t value)
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{
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__ASM volatile("csrw mscratch, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MEPC
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*
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* @brief Return the Machine Exception Program Register
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*
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* @return mepc value
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*/
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uint32_t RISCV_get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mepc" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MEPC
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*
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* @brief Set the Machine Exception Program Register
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*
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* @return mepc value
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*/
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void RISCV_set_MEPC(uint32_t value)
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{
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__ASM volatile("csrw mepc, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MCAUSE
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*
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* @brief Return the Machine Cause Register
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*
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* @return mcause value
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*/
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uint32_t RISCV_get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mcause": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MEPC
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*
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* @brief Set the Machine Cause Register
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*
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* @return mcause value
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*/
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void RISCV_set_MCAUSE(uint32_t value)
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{
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__ASM volatile("csrw mcause, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MTVAL
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*
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* @brief Return the Machine Trap Value Register
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*
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* @return mtval value
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*/
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uint32_t RISCV_get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtval" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_set_MTVAL
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*
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* @brief Set the Machine Trap Value Register
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*
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* @return mtval value
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*/
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void RISCV_set_MTVAL(uint32_t value)
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{
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__ASM volatile("csrw mtval, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn RISCV_get_MVENDORID
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*
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* @brief Return Vendor ID Register
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*
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* @return mvendorid value
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*/
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uint32_t RISCV_get_MVENDORID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mvendorid": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_get_MARCHID
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*
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* @brief Return Machine Architecture ID Register
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*
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* @return marchid value
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*/
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uint32_t RISCV_get_MARCHID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""marchid": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_get_MIMPID
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*
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* @brief Return Machine Implementation ID Register
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*
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* @return mimpid value
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*/
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uint32_t RISCV_get_MIMPID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mimpid": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_get_MHARTID
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*
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* @brief Return Hart ID Register
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*
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* @return mhartid value
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*/
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uint32_t RISCV_get_MHARTID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mhartid": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn RISCV_get_SP
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*
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* @brief Return SP Register
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*
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* @return SP value
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*/
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uint32_t RISCV_get_SP(void)
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{
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uint32_t result;
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__ASM volatile("mv %0,""sp": "=r"(result):);
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return (result);
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}
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