diff --git a/CPU/QingKeV3/os_port.c b/CPU/QingKeV3/os_port.c
index b8b498b..706fc10 100644
--- a/CPU/QingKeV3/os_port.c
+++ b/CPU/QingKeV3/os_port.c
@@ -124,9 +124,7 @@ void os_port_restore_irq(os_uint_t level){
 }
 
 os_uint_t os_port_save_disable_irq_in_isr(void){
-    os_uint_t level = RISCV_get_MSTATUS();
-    RISCV_set_MSTATUS(0x1800);
-    return level;
+    return RISCV_get_set_MSTATUS(0x1800);
 }
 
 void os_port_restore_irq_in_isr(os_uint_t level){
diff --git a/CPU/QingKeV3/os_port_gnu.S b/CPU/QingKeV3/os_port_gnu.S
index 2b4c104..f8affa1 100644
--- a/CPU/QingKeV3/os_port_gnu.S
+++ b/CPU/QingKeV3/os_port_gnu.S
@@ -132,7 +132,9 @@ os_port_context_restore:
     lw a0,   0 * 4(sp)
     csrw mepc, a0
 
-    lw  a0,  2*4(sp)        /* 恢复 MPIE */
+    li t0, 0x1800
+    csrs mstatus, t0
+    lw  a0,  2*4(sp)
     csrs  mstatus, a0
 
     lw x1,   1 * 4(sp)      /* 返回地址 */
diff --git a/CPU/QingKeV3/riscv.c b/CPU/QingKeV3/riscv.c
index d084634..ab3051b 100644
--- a/CPU/QingKeV3/riscv.c
+++ b/CPU/QingKeV3/riscv.c
@@ -20,6 +20,15 @@ uint32_t RISCV_get_MSTATUS(void)
     return (result);
 }
 
+uint32_t RISCV_get_set_MSTATUS(uint32_t value){
+    uint32_t result;
+    __ASM volatile("csrrw %0, mstatus, %1"
+        : "=r"(result)
+        :"r"(value)
+        :"memory");
+    return (result);
+}
+
 /*********************************************************************
  * @fn      RISCV_set_MSTATUS
  *
diff --git a/CPU/QingKeV3/riscv.h b/CPU/QingKeV3/riscv.h
index 55b0c9d..dfd1eaa 100644
--- a/CPU/QingKeV3/riscv.h
+++ b/CPU/QingKeV3/riscv.h
@@ -216,6 +216,7 @@ int32_t RISCV_AMOXOR_W(volatile int32_t *addr, int32_t value)
 /* ------------------------------------------------------------------------------------------------------------------ */
 /*  */
 
+extern uint32_t RISCV_get_set_MSTATUS(uint32_t value);
 extern uint32_t RISCV_get_MSTATUS(void);
 extern void RISCV_set_MSTATUS(uint32_t value);
 extern uint32_t RISCV_get_MISA(void);