PORT按CPU型号更简单
This commit is contained in:
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#include <riscv.h>
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volatile uint32_t QK_WFE_MASK = 0;
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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/*********************************************************************
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* @fn __get_FFLAGS
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*
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* @brief Return the Floating-Point Accrued Exceptions
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*
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* @return fflags value
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*/
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uint32_t RISCV_get_FFLAGS(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_FFLAGS
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*
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* @brief Set the Floating-Point Accrued Exceptions
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*
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* @param value - set FFLAGS value
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*
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* @return none
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*/
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void RISCV_set_FFLAGS(uint32_t value)
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{
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__ASM volatile ("csrw fflags, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_FRM
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*
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* @brief Return the Floating-Point Dynamic Rounding Mode
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*
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* @return frm value
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*/
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uint32_t RISCV_get_FRM(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "frm" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_FRM
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*
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* @brief Set the Floating-Point Dynamic Rounding Mode
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*
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* @param value - set frm value
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*
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* @return none
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*/
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void RISCV_set_FRM(uint32_t value)
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{
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__ASM volatile ("csrw frm, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_FCSR
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*
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* @brief Return the Floating-Point Control and Status Register
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*
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* @return fcsr value
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*/
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uint32_t RISCV_get_FCSR(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_FCSR
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*
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* @brief Set the Floating-Point Dynamic Rounding Mode
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*
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* @param value - set fcsr value
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*
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* @return none
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*/
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void RISCV_set_FCSR(uint32_t value)
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{
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__ASM volatile ("csrw fcsr, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MSTATUS
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*
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* @brief Return the Machine Status Register
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*
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* @return mstatus value
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*/
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uint32_t RISCV_get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSTATUS
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*
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* @brief Set the Machine Status Register
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*
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* @param value - set mstatus value
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*
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* @return none
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*/
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void RISCV_set_MSTATUS(uint32_t value)
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{
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__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MISA
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*
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* @brief Return the Machine ISA Register
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*
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* @return misa value
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*/
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uint32_t RISCV_get_MISA(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set misa value
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*
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* @return none
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*/
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void RISCV_set_MISA(uint32_t value)
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{
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__ASM volatile ("csrw misa, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MTVEC
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*
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* @brief Return the Machine Trap-Vector Base-Address Register
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*
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* @return mtvec value
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*/
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uint32_t RISCV_get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVEC
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*
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* @brief Set the Machine Trap-Vector Base-Address Register
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*
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* @param value - set mtvec value
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*
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* @return none
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*/
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void RISCV_set_MTVEC(uint32_t value)
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{
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__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MSCRATCH
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*
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* @brief Return the Machine Seratch Register
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*
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* @return mscratch value
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*/
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uint32_t RISCV_get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSCRATCH
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*
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* @brief Set the Machine Seratch Register
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*
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* @param value - set mscratch value
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*
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* @return none
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*/
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void RISCV_set_MSCRATCH(uint32_t value)
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{
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__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MEPC
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*
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* @brief Return the Machine Exception Program Register
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*
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* @return mepc value
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*/
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uint32_t RISCV_get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Exception Program Register
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*
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* @return mepc value
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*/
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void RISCV_set_MEPC(uint32_t value)
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{
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__ASM volatile ("csrw mepc, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MCAUSE
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*
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* @brief Return the Machine Cause Register
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*
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* @return mcause value
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*/
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uint32_t RISCV_get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Cause Register
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*
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* @return mcause value
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*/
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void RISCV_set_MCAUSE(uint32_t value)
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{
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__ASM volatile ("csrw mcause, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MTVAL
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*
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* @brief Return the Machine Trap Value Register
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*
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* @return mtval value
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*/
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uint32_t RISCV_get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVAL
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*
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* @brief Set the Machine Trap Value Register
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*
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* @return mtval value
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*/
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void RISCV_set_MTVAL(uint32_t value)
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{
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__ASM volatile ("csrw mtval, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MVENDORID
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*
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* @brief Return Vendor ID Register
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*
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* @return mvendorid value
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*/
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uint32_t RISCV_get_MVENDORID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __get_MARCHID
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*
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* @brief Return Machine Architecture ID Register
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*
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* @return marchid value
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*/
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uint32_t RISCV_get_MARCHID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __get_MIMPID
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*
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* @brief Return Machine Implementation ID Register
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*
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* @return mimpid value
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*/
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uint32_t RISCV_get_MIMPID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __get_MHARTID
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*
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* @brief Return Hart ID Register
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*
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* @return mhartid value
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*/
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uint32_t RISCV_get_MHARTID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
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return (result);
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}
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/*********************************************************************
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* @fn __get_SP
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*
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* @brief Return SP Register
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*
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* @return SP value
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*/
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uint32_t RISCV_get_SP(void)
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{
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uint32_t result;
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__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MCOUNT_INHIBIT
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*
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* @brief Set Instruction and cycle count shield switch in machine mode
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*
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* @return mcause value
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*/
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void RISCV_set_MCOUNT_INHIBIT(uint32_t value)
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{
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__ASM volatile ("csrw mcounteren, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MCOUNT_INHIBIT
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*
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* @brief Return Instruction and cycle count shield switch in machine mode
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*
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* @return SP value
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*/
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uint32_t RISCV_get_MCOUNT_INHIBIT(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcounteren" : "=r"(result) : );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MCYCLE
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*
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* @brief Set the number of cycles in machine mode
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*
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* @return mcause value
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*/
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void RISCV_set_MCYCLE(uint32_t value)
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{
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__ASM volatile ("csrw mcycle, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MCYCLE
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*
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* @brief Return the number of cycles in machine mode
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*
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* @return SP value
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*/
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uint32_t RISCV_get_MCYCLE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcycle" : "=r"(result) : );
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return (result);
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}
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/*********************************************************************
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* @fn __set_MINSTRET
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*
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* @brief Set the number of completed instructions in machine mode
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*
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* @return mcause value
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*/
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void RISCV_set_MINSTRET(uint32_t value)
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{
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__ASM volatile ("csrw minstret, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_MINSTRET
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*
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* @brief Return the number of completed instructions in machine mode
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*
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* @return SP value
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*/
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uint32_t RISCV_get_MINSTRET(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "minstret" : "=r"(result) : );
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return (result);
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}
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/*********************************************************************
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* @fn __set_UCYCLE
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*
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* @brief Set the number of cycles in user mode
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*
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* @return mcause value
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*/
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void RISCV_set_UCYCLE(uint32_t value)
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{
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__ASM volatile ("csrw cycle, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_UCYCLE
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*
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* @brief Return the number of cycles in user mode
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*
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* @return SP value
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*/
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uint32_t RISCV_get_UCYCLE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "cycle" : "=r"(result) : );
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return (result);
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}
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/*********************************************************************
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* @fn __set_UINSTRET
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*
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* @brief Set the number of completed instructions in user mode
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*
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* @return mcause value
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*/
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void RISCV_set_UINSTRET(uint32_t value)
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{
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__ASM volatile ("csrw instret, %0" : : "r" (value) );
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}
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/*********************************************************************
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* @fn __get_UINSTRET
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*
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* @brief Return the number of completed instructions in user mode
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*
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* @return SP value
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*/
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uint32_t RISCV_get_UINSTRET(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "instret" : "=r"(result) : );
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return (result);
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}
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/* ------------------------------------------------------------------------------------------------------------------ */
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/* HSEM */
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/* HSEM Key */
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#define QK_HSEM_KEY (0x5AA50000)
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/*********************************************************************
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* @fn HSEM_Take
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*
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* @brief Take a semaphore in 2 Step mode.
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*
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* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
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* ProcessID - Process ID from 0 to 255.
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*
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* @return READY - Take success.
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* NoREADY - Take error.
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*/
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QK_ErrorStatus QK_HSEM_Take(QK_HSEM_ID_TypeDef HSEM_ID, uint32_t ProcessID)
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{
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QK_ErrorStatus status = QK_NoREADY;
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QK_HSEM->RX[HSEM_ID] = ((ProcessID & 0xFF) | ((QK_NVIC_GetCurrentCoreID() << 8) | (1 << 31)));
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if( QK_HSEM->RX[HSEM_ID] == ((ProcessID & 0xFF) | ((QK_NVIC_GetCurrentCoreID() << 8) | (1 << 31))))
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{
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status = QK_READY;
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}
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else
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{
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status = QK_NoREADY;
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}
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return (status);
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}
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|
||||
/*********************************************************************
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||||
* @fn HSEM_FastTake
|
||||
*
|
||||
* @brief Fast Take a semaphore with 1 Step mode.
|
||||
*
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* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
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* @return READY - Take success.
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* NoREADY - Take error.
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*/
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QK_ErrorStatus QK_HSEM_FastTake(QK_HSEM_ID_TypeDef HSEM_ID)
|
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{
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QK_ErrorStatus status = QK_NoREADY;
|
||||
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if( QK_HSEM->RLRX[HSEM_ID] == ((QK_NVIC_GetCurrentCoreID() << 8) | (1 << 31)))
|
||||
{
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||||
status = QK_READY;
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}
|
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else
|
||||
{
|
||||
status = QK_NoREADY;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_GetOneSemTakenState
|
||||
*
|
||||
* @brief Get one semaphore state Taken or not.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
|
||||
* @return ENABLE - Take.
|
||||
* DISABLE - No Take.
|
||||
*/
|
||||
QK_FunctionalState QK_HSEM_GetOneSemTakenState(QK_HSEM_ID_TypeDef HSEM_ID)
|
||||
{
|
||||
QK_FunctionalState status = QK_DISABLE;
|
||||
|
||||
if( (QK_HSEM->RX[HSEM_ID] & (1 << 31)) == (1 << 31))
|
||||
{
|
||||
status = QK_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = QK_DISABLE;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_GetAllSemTakenState
|
||||
*
|
||||
* @brief Get all semaphore state Taken or not.
|
||||
*
|
||||
* @return All semaphore state Taken or not.
|
||||
*/
|
||||
uint32_t QK_HSEM_GetAllSemTakenState(void)
|
||||
{
|
||||
return (QK_HSEM->LSE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_OwnCoreGetAllSemTakenState
|
||||
*
|
||||
* @brief Its own core(V3F or V5F) get all semaphore state Taken or not.
|
||||
*
|
||||
* @return All semaphore state Taken or not for own core(V3F or V5F) .
|
||||
*/
|
||||
uint32_t QK_HSEM_OwnCoreGetAllSemTakenState(void)
|
||||
{
|
||||
return (QK_HSEM->LSM);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ReleaseOneSem
|
||||
*
|
||||
* @brief Release one semaphore.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
* ProcessID - Process ID from 0 to 255.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ReleaseOneSem(QK_HSEM_ID_TypeDef HSEM_ID, uint32_t ProcessID)
|
||||
{
|
||||
QK_HSEM->RX[HSEM_ID] = (ProcessID & 0xFF) | ((QK_NVIC_GetCurrentCoreID() << 8));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ReleaseAllSem
|
||||
*
|
||||
* @brief Release all semaphore.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ReleaseAllSem(void)
|
||||
{
|
||||
QK_HSEM->CLR = QK_HSEM_KEY | (1<<13) | (1<<12);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ReleaseSem_MatchCID_PID
|
||||
*
|
||||
* @brief Release semaphore that matches the ProcessID and CoreID.
|
||||
*
|
||||
* @param CoreID - core ID.
|
||||
* HSEM_Core_ID_V3F - Riscv V3F
|
||||
* HSEM_Core_ID_V5F - Riscv V5F
|
||||
* ProcessID - Process ID from 0 to 255.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ReleaseSem_MatchCID_PID(uint32_t CoreID, uint32_t ProcessID)
|
||||
{
|
||||
QK_HSEM->CLR = QK_HSEM_KEY | CoreID | (ProcessID & 0xFF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ReleaseSem_MatchCID
|
||||
*
|
||||
* @brief Release semaphore that matches the CoreID.
|
||||
*
|
||||
* @param CoreID - core ID.
|
||||
* HSEM_Core_ID_V3F - Riscv V3F
|
||||
* HSEM_Core_ID_V5F - Riscv V5F
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ReleaseSem_MatchCID(uint32_t CoreID )
|
||||
{
|
||||
QK_HSEM->CLR = QK_HSEM_KEY | CoreID | (1<<12);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ReleaseSem_MatchPID
|
||||
*
|
||||
* @brief Release semaphore that matches the ProcessID and CoreID.
|
||||
*
|
||||
* @param ProcessID - Process ID from 0 to 255.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ReleaseSem_MatchPID(uint32_t ProcessID)
|
||||
{
|
||||
QK_HSEM->CLR = QK_HSEM_KEY | (ProcessID & 0xFF) | (1<<13);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_SetClearKey
|
||||
*
|
||||
* @brief Set semaphore Key.
|
||||
*
|
||||
* @param Key - semaphore key value from 0 to 0xFFFF.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_SetClearKey(uint32_t Key)
|
||||
{
|
||||
QK_HSEM->CLR = (Key << 16);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_GetClearKey
|
||||
*
|
||||
* @brief Get semaphore Key.
|
||||
*
|
||||
* @return semaphore key value from 0 to 0xFFFF.
|
||||
*/
|
||||
uint32_t QK_HSEM_GetClearKey(void)
|
||||
{
|
||||
return ((QK_HSEM->KEY >> 16));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the HSEM interrupts.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ITConfig(QK_HSEM_ID_TypeDef HSEM_ID, QK_FunctionalState NewState)
|
||||
{
|
||||
if(NewState != QK_DISABLE)
|
||||
{
|
||||
QK_HSEM->IER |= (1 << HSEM_ID);
|
||||
}
|
||||
else
|
||||
{
|
||||
QK_HSEM->IER &= (~(uint32_t)(1 << HSEM_ID));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified HSEM flag is set or not.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
QK_FlagStatus QK_HSEM_GetFlagStatus(QK_HSEM_ID_TypeDef HSEM_ID)
|
||||
{
|
||||
QK_FlagStatus bitstatus = QK_RESET;
|
||||
|
||||
if((QK_HSEM->ISR & (1<<HSEM_ID)) != (uint32_t)QK_RESET)
|
||||
{
|
||||
bitstatus = QK_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = QK_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ClearFlag
|
||||
*
|
||||
* @brief Clears the HSEM's pending flags.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ClearFlag(QK_HSEM_ID_TypeDef HSEM_ID)
|
||||
{
|
||||
QK_HSEM->ISR = (1<<HSEM_ID);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified HSEM interrupt has occurred or not.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
QK_ITStatus QK_HSEM_GetITStatus(QK_HSEM_ID_TypeDef HSEM_ID)
|
||||
{
|
||||
QK_ITStatus bitstatus = QK_RESET;
|
||||
|
||||
if(((QK_HSEM->ISM & (1<<HSEM_ID)) != (uint32_t)QK_RESET))
|
||||
{
|
||||
bitstatus = QK_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = QK_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HSEM_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the HSEM's interrupt pending bits.
|
||||
*
|
||||
* @param HSEM_ID - pointer to a HSEM_ID_TypeDef structure.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void QK_HSEM_ClearITPendingBit(QK_HSEM_ID_TypeDef HSEM_ID)
|
||||
{
|
||||
QK_HSEM->ISR = (1<<HSEM_ID);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user