移植到 CH32V10x 既 QingKeV3 系列 MCU 上

2026-05-22 18:13:11 +08:00
parent bdfd09eca8
commit 80e32d4fb8
14 changed files with 1194 additions and 7 deletions
@@ -0,0 +1,278 @@
+#include <riscv.h>
+
+#define __ASM       __asm     /*  asm keyword for GNU Compiler          */
+#define __INLINE    inline    /*  inline keyword for GNU Compiler       */
+
+
+
+/*********************************************************************
+ * @fn      RISCV_get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t RISCV_get_MSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mstatus": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void RISCV_set_MSTATUS(uint32_t value)
+{
+    __ASM volatile("csrw mstatus, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t RISCV_get_MISA(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""misa" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set misa value
+ *
+ * @return  none
+ */
+void RISCV_set_MISA(uint32_t value)
+{
+    __ASM volatile("csrw misa, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t RISCV_get_MTVEC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mtvec": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void RISCV_set_MTVEC(uint32_t value)
+{
+    __ASM volatile("csrw mtvec, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MSCRATCH
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t RISCV_get_MSCRATCH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mscratch" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MSCRATCH
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void RISCV_set_MSCRATCH(uint32_t value)
+{
+    __ASM volatile("csrw mscratch, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t RISCV_get_MEPC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mepc" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void RISCV_set_MEPC(uint32_t value)
+{
+    __ASM volatile("csrw mepc, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t RISCV_get_MCAUSE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mcause": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void RISCV_set_MCAUSE(uint32_t value)
+{
+    __ASM volatile("csrw mcause, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MTVAL
+ *
+ * @brief   Return the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+uint32_t RISCV_get_MTVAL(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mtval" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_set_MTVAL
+ *
+ * @brief   Set the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+void RISCV_set_MTVAL(uint32_t value)
+{
+    __ASM volatile("csrw mtval, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t RISCV_get_MVENDORID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mvendorid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t RISCV_get_MARCHID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""marchid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t RISCV_get_MIMPID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mimpid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t RISCV_get_MHARTID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mhartid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      RISCV_get_SP
+ *
+ * @brief   Return SP Register
+ *
+ * @return  SP value
+ */
+uint32_t RISCV_get_SP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("mv %0,""sp": "=r"(result):);
+    return (result);
+}